Flash memory with multiple status reading capability

ABSTRACT

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

TECHNICAL FIELD OF THE INVENTION

This application is a divisional of U.S. patent application Ser. No.09/609,037, now U.S. Pat. No. 6,442,076, filed Jun. 30, 2000 and titled,“Flash Memory with Multiple Status Reading Capability,” which iscommonly assigned and incorporated herein by reference.

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal storage areas in thecomputer. The term memory identifies data storage that comes in the formof integrated circuit chips. There are several different types ofmemory. One type is RAM (random-access memory). This is typically usedas main memory in a computer environment. RAM refers to read and writememory; that is, you can both write data into RAM and read data fromRAM. This is in contrast to ROM, which permits you only to read data.Most RAM is volatile, which means that it requires a steady flow ofelectricity to maintain its contents. As soon as the power is turnedoff, whatever data was in RAM is lost.

Computers almost always contain a small amount of read-only memory (ROM)that holds instructions for starting up the computer. Unlike RAM, ROMcannot be written to. An EEPROM (electrically erasable programmableread-only memory) is a special type non-volatile ROM that can be erasedby exposing it to an electrical charge. Like other types of ROM, EEPROMis traditionally not as fast as RAM. EEPROM comprise a large number ofmemory cells having electrically isolated gates (floating gates). Datais stored in the memory cells in the form of charge on the floatinggates. Charge is transported to or removed from the floating gates byprogramming and erase operations, respectively.

Yet another type of non-volatile memory is a Flash memory. A Flashmemory is a type of EEPROM that can be erased and reprogrammed in blocksinstead of one byte at a time. Many modem PCS have their BIOS stored ona flash memory chip so that it can easily be updated if necessary. Sucha BIOS is sometimes called a flash BIOS. Flash memory is also popular inmodems because it enables the modem manufacturer to support newprotocols as they become standardized.

A typical Flash memory comprises a memory array that includes a largenumber of memory cells arranged in row and column fashion. Each of thememory cells includes a floating gate field-effect transistor capable ofholding a charge. The cells are usually grouped into blocks. Each of thecells within a block can be electrically programmed in a random basis bycharging the floating gate. The charge can be removed from the floatinggate by a block erase operation. The data in a cell is determined by thepresence or absence of the charge in the floating gate.

A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higherclock speeds than conventional DRAM memory. SDRAM synchronizes itselfwith a CPU's bus and is capable of running at 100 MHZ, about three timesfaster than conventional FPM (Fast Page Mode) RAM, and about twice asfast EDO (Extended Data Output) DRAM and BEDO (Burst Extended DataOutput) DRAM. SDRAM's can be accessed quickly, but are volatile. Manycomputer systems are designed to operate using SDRAM, but would benefitfrom non-volatile memory.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora non-volatile memory device that can operate in a manner similar toSDRAM operation. Further, there is a need for a synchronous memory thatcan provide multiple status reading options.

SUMMARY OF THE INVENTION

The above-mentioned problems with memory devices and other problems areaddressed by the present invention and will be understood by reading andstudying the following specification.

In one embodiment, a method of operating a memory device comprisesinitiating a write operation on a first block of an array of memorycells, initiating a first read operation on the first block during thewrite operation, and automatically outputting a write status in responseto initiating the first read operation. The write status indicates thatthe write operation is being performed on the first block.

In another embodiment, a method of controlling a memory device comprisesexecuting a write operation on a first addressable block of an array ofmemory cells, and setting a bank register to a first state while thewrite operation is being performed. The first state indicates that thefirst block is being written to. The method further comprises initiatinga first read operation in response to a read command received duringexecution of the write operation, comparing a read address provided withthe read command to the bank register, and automatically outputting awrite status in response to the read command if the read address islocated in the first block. The write status indicates that the writeoperation is being performed on the first block.

In yet another embodiment, a method of controlling a memory devicecomprises coupling a write command, a write address and write data froma first processor to the memory device, and executing a write operationon a first addressable block of an array of memory cells. The firstaddressable block corresponds to the write address. A bank register isset to a first state while the write operation is being executed,wherein the first state indicates that the first block is being writtento. The method includes coupling a read command and a read address froma second processor to the memory device, initiating a first readoperation in response to a read command received during execution of thewrite operation, comparing the read address provided with the readcommand to the bank register, and automatically outputting a writestatus in response to the read command if the read address correspondsto the first block. Again, the write status indicates that the writeoperation is being executed on the first block.

A memory device is provided in one embodiment that comprises an array ofmemory cells arranged in a plurality of addressable blocks, a bankregister having a plurality of bits corresponding to the plurality ofblocks, and an array status register to store status data indicatingwhere a write operation is performed on the array. Control circuitry isprovided to perform a write operation on a first block of the pluralityof blocks and automatically couple the status data to external dataconnections in response to a read command.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram of a synchronous flash memory of the presentinvention;

FIG. 1B is an integrated circuit pin interconnect diagram of oneembodiment of the present invention;

FIG. 1C is an integrated circuit interconnect bump grid array diagram ofone embodiment of the present invention;

FIG. 2 illustrates a mode register of one embodiment of the presentinvention;

FIG. 3 illustrates read operations having a CAS latency of one, two andthree clock cycles;

FIG. 4 illustrates activating a specific row in a bank of the memory ofone embodiment of the present invention;

FIG. 5 illustrates timing between an active command and a read or writecommand;

FIG. 6 illustrates a read command;

FIG. 7 illustrates timing for consecutive read bursts of one embodimentof the present invention;

FIG. 8 illustrates random read accesses within a page of one embodimentof the present invention;

FIG. 9 illustrates a read operation followed by a write operation;

FIG. 10 illustrates read burst operation that are terminated using aburst terminate command according to one embodiment of the presentinvention;

FIG. 11 illustrates a write command;

FIG. 12 illustrates a write followed by a read operation;

FIG. 13 illustrates a power-down operation of one embodiment of thepresent invention;

FIG. 14 illustrates a clock suspend operation during a burst read;

FIG. 15 illustrates a memory address map of one embodiment of the memoryhaving two boot sectors;

FIG. 16 is a flow chart of a self-timed write sequence according to oneembodiment of the present invention;

FIG. 17 is a flow chart of a complete write status-check sequenceaccording to one embodiment of the present invention;

FIG. 18 is a flow chart of a self-timed block erase sequence accordingto one embodiment of the present invention;

FIG. 19 is a flow chart of a complete block erase status-check sequenceaccording to one embodiment of the present invention;

FIG. 20 is a flow chart of a block protect sequence according to oneembodiment of the present invention;

FIG. 21 is a flow chart of a complete block status-check sequenceaccording to one embodiment of the present invention;

FIG. 22 is a flow chart of a device protect sequence according to oneembodiment of the present invention;

FIG. 23 is a flow chart of a block unprotect sequence according to oneembodiment of the present invention;

FIG. 24 illustrates the timing of an initialize and load mode registeroperation;

FIG. 25 illustrates the timing of a clock suspend mode operation;

FIG. 26 illustrates the timing of a burst read operation;

FIG. 27 illustrates the timing of alternating bank read accesses;

FIG. 28 illustrates the timing of a full-page burst read operation;

FIG. 29 illustrates the timing of a burst read operation using a datamask signal;

FIG. 30 illustrates the timing of a write operation followed by a readto a different bank;

FIG. 31 illustrates the timing of a write operation followed by a readto the same bank;

FIG. 32 illustrates a memory system of the present invention; and

FIG. 33 illustrates a multi-processor system of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of present embodiments, referenceis made to the accompanying drawings that form a part hereof, and inwhich is shown by way of illustration specific embodiments in which theinventions may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that logical, mechanical and electrical changes may be madewithout departing from the spirit and scope of the present invention.The following detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the claims.

The following detailed description is divided into two major sections.The first section is an Interface Functional Description that detailscompatibility with an SDRAM memory. The second major section is aFunctional Description that specifies flash architecture functionalcommands.

Interface Functional Description

Referring to FIG. 1A, a block diagram of one embodiment of the presentinvention is described. The memory device 100 includes an array ofnon-volatile flash memory cells 102. The array is arranged in aplurality of addressable banks. In one embodiment, the memory containsfour memory banks 104, 106, 108 and 110. Each memory bank containsaddressable sectors of memory cells. The data stored in the memory canbe accessed using externally provided location addresses received byaddress register 112. The addresses are decoded using row addressmultiplexer circuitry 114. The addresses are also decoded using bankcontrol logic 116 and row address latch and decode circuitry 118. Toaccess an appropriate column of the memory, column address counter andlatch circuitry 120 couples the received addresses to column decodecircuitry 122. Circuit 124 provides input/output gating, data masklogic, read data latch circuitry and write driver circuitry. Data isinput through data input registers 126 and output through data outputregisters 128. Command execution logic 130 is provided to control thebasic operations of the memory device. A state machine 132 is alsoprovided to control specific operations performed on the memory arraysand cells. A status register 134 and an identification register 136 canalso be provided to output data.

FIG. 1B illustrates an interconnect pin assignment of one embodiment ofthe present invention. The memory package 150 has 54 interconnect pins.The pin configuration is substantially similar to available SDRAMpackages. Two interconnects specific to the present invention are RP#152 and Vccp 154. Although the present invention may share interconnectlabels that are appear the same as SDRAM's, the function of the signalsprovided on the interconnects are described herein and should not beequated to SDRAM's unless set forth herein. FIG. 1C illustrates oneembodiment of a memory package 160 that has bump connections instead ofthe pin connections of FIG. 1C. The present invention, therefore, is notlimited to a specific package configuration.

Prior to describing the operational features of the memory device, amore detailed description of the interconnect pins and their respectivesignals is provided.

The input clock connection is used to provide a clock signal (CLK). Theclock signal can be driven by a system clock, and all synchronous flashmemory input signals are sampled on the positive edge of CLK. CLK alsoincrements an internal burst counter and controls the output registers.

The input clock enable (CKE) connection is used to activate (HIGH state)and deactivates (LOW state) the CLK signal input. Deactivating the clockinput provides POWER-DOWN and STANDBY operation (where all memory banksare idle), ACTIVE POWER-DOWN (a memory row is ACTIVE in either bank) orCLOCK SUSPEND operation (burst/access in progress). CKE is synchronousexcept after the device enters power-down modes, where CKE becomesasynchronous until after exiting the same mode. The input buffers,including CLK, are disabled during power-down modes to provide lowstandby power. CKE may be tied HIGH in systems where power-down modes(other than RP# deep power-down) are not required.

The chip select (CS#) input connection provides a signal to enable(registered LOW) and disable (registered HIGH) a command decoderprovided in the command execution logic. All commands are masked whenCS# is registered HIGH. Further, CS# provides for external bankselection on systems with multiple banks, and CS# can be considered partof the command code; but may not be necessary.

The input command input connections for RAS#, CAS#, and WE# (along withCAS#, CS#) define a command that is to be executed by the memory, asdescribed in detail below. The input/output mask (DQM) connections areused to provide input mask signals for write accesses and an outputenable signal for read accesses. Input data is masked when DQM issampled HIGH during a WRITE cycle. The output buffers are placed in ahigh impedance (High-Z) state (after a two-clock latency) when DQM issampled HIGH during a READ cycle. DQML corresponds to data connectionsDQ0-DQ7 and DQMH corresponds to data connections DQ8-DQ15. DQML and DQMHare considered to be the same state when referenced as DQM.

Address inputs 133 are primarily used to provide address signals. In theillustrated embodiment the memory has 12 lines (A0-A11). Other signalscan be provided on the address connections, as described below. Theaddress inputs are sampled during an ACTIVE command (row-address A0-A11)and a READ/WRITE command (column-address A0-A7) to select one locationin a respective memory bank. The address inputs are also used to providean operating code (OpCode) during a LOAD COMMAND REGISTER operation,explained below. Address lines A0-A11 are also used to input modesettings during a LOAD MODE REGISTER operation.

An input reset/power-down (RP#) connection 140 is used for reset andpower-down operations. Upon initial device power-up, a 100 μs delayafter RP# has transitioned from LOW to HIGH is required in oneembodiment for internal device initialization, prior to issuing anexecutable command. The RP# signal clears the status register, sets theinternal state machine (ISM) 132 to an array read mode, and places thedevice in a deep power-down mode when LOW. During power down, all inputconnections, including CS# 142, are “Don't Care” and all outputs areplaced in a High-Z state. When the RP# signal is equal to a VHH voltage(5V), all protection modes are ignored during WRITE and ERASE. The RP#signal also allows a device protect bit to be set to 1 (protected) andallows block protect bits of a 16 bit register, at locations 0 and 15 tobe set to 0 (unprotected) when brought to VHH. The protect bits aredescribed in more detail below. RP# is held HIGH during all other modesof operation.

Bank address input connections, BA0 and BA1 define which bank an ACTIVE,READ, WRITE, or BLOCK PROTECT command is being applied. The DQ0-DQ15connections 143 are data bus connections used for bi-directional datacommunication. Referring to FIG. 1B, a VCCQ connection is used toprovide isolated power to the DQ connections to improved noise immunity.In one embodiment, VCCQ=Vcc or 1.8V±0.15V. The VSSQ connection is usedto isolated ground to DQs for improved noise immunity. The VCCconnection provides a power supply, such as 3V. A ground connection isprovided through the Vss connection. Another optional voltage isprovided on the VCCP connection 144. The VCCP connection can be tiedexternally to VCC, and sources current during device initialization,WRITE and ERASE operations. That is, writing or erasing to the memorydevice can be performed using a VCCP voltage, while all other operationscan be performed with a VCC voltage. The Vccp connection is coupled to ahigh voltage switch/pump circuit 145.

The following sections provide a more detailed description of theoperation of the synchronous flash memory. One embodiment of the presentinvention is a nonvolatile, electrically sector-erasable (Flash),programmable read-only memory containing 67,108,864 bits organized as4,194,304 words by 16 bits. Other population densities are contemplated,and the present invention is not limited to the example density. Eachmemory bank is organized into four independently erasable blocks (16total). To ensure that critical firmware is protected from accidentalerasure or overwrite, the memory can include sixteen 256K-word hardwareand software lockable blocks. The memory's four-bank architecturesupports true concurrent operations.

A read access to any bank can occur simultaneously with a backgroundWRITE or ERASE operation to any other bank. The synchronous flash memoryhas a synchronous interface (all signals are registered on the positiveedge of the clock signal, CLK). Read accesses to the memory can be burstoriented. That is, memory accesses start at a selected location andcontinue for a programmed number of locations in a programmed sequence.Read accesses begin with the registration of an ACTIVE command, followedby a READ command. The address bits registered coincident with theACTIVE command are used to select the bank and row to be accessed. Theaddress bits registered coincident with the READ command are used toselect the starting column location and bank for the burst access.

The synchronous flash memory provides for programmable read burstlengths of 1, 2, 4 or 8 locations, or the full page, with a burstterminate option. Further, the synchronous flash memory uses an internalpipelined architecture to achieve high-speed operation.

The synchronous flash memory can operate in low-power memory systems,such as systems operating on three volts. A deep power-down mode isprovided, along with a power-saving standby mode. All inputs and outputsare low voltage transistor-transistor logic (LVTTL) compatible. Thesynchronous flash memory offers substantial advances in Flash operatingperformance, including the ability to synchronously burst data at a highdata rate with automatic column address generation and the capability torandomly change column addresses on each clock cycle during a burstaccess.

In general, the synchronous flash memory is configured similar to amulti-bank DRAM that operates at low voltage and includes a synchronousinterface. Each of the banks is organized into rows and columns. Priorto normal operation, the synchronous flash memory is initialized. Thefollowing sections provide detailed information covering deviceinitialization, register definition, command descriptions and deviceoperation.

The synchronous flash is powered up and initialized in a predefinedmanner. After power is applied to VCC, VCCQ and VCCP (simultaneously),and the clock signal is stable, RP# 140 is brought from a LOW state to aHIGH state. A delay, such as a 100 μs is delay, is needed after RP#transitions HIGH in order to complete internal device initialization.After the delay time has passed, the memory is placed in an array readmode and is ready for Mode Register programming or an executablecommand. After initial programming of a non-volatile mode register 147(NVMode Register), the contents are automatically loaded into a volatileMode Register 148 during the initialization. The device will power up ina programmed state and will not require reloading of the non-volatilemode register 147 prior to issuing operational commands. This isexplained in greater detail below.

The Mode Register 148 is used to define the specific mode of operationof the synchronous flash memory. This definition includes the selectionof a burst length, a burst type, a CAS latency, and an operating mode,as shown in FIG. 2. The Mode Register is programmed via a LOAD MODEREGISTER command and retains stored information until it isreprogrammed. The contents of the Mode Register may be copied into theNVMode Register 147. The NVMode Register settings automatically load theMode Register 148 during initialization. Details on ERASE NVMODEREGISTER and WRITE NVMODE REGISTER command sequences are provided below.Those skilled in the art will recognize that an SDRAM requires that amode register must be externally loaded during each initializationoperation. The present invention allows a default mode to be stored inthe NV mode register 147. The contents of the NV mode register are thencopied into a volatile mode register 148 for access during memoryoperations.

Mode Register bits M0-M2 specify a burst length, M3 specifies a bursttype (sequential or interleaved), M4-M6 specify a CAS latency, M7 and M8specify a operating mode, M9 is set to one, and M10 and M11 are reservedin this embodiment. Because WRITE bursts are not currently implemented,M9 is set to a logic one and write accesses are single location(non-burst) accesses. The Mode Register must be loaded when all banksare idle, and the controller must wait the specified time beforeinitiating a subsequent operation.

Read accesses to the synchronous flash memory can be burst oriented,with the burst length being programmable, as shown in Table 1. The burstlength determines the maximum number of column locations that can beautomatically accessed for a given READ command. Burst lengths of 1, 2,4, or 8 locations are available for both sequential and the interleavedburst types, and a full-page burst is available for the sequential type.The full-page burst can be used in conjunction with the BURST TERMINATEcommand to generate arbitrary burst lengths that is, a burst can beselectively terminated to provide custom length bursts. When a READcommand is issued, a block of columns equal to the burst length iseffectively selected. All accesses for that burst take place within thisblock, meaning that the burst will wrap within the block if a boundaryis reached. The block is uniquely selected by A1-A7 when the burstlength is set to two, by A2-A7 when the burst length is set to four, andby A3-A7 when the burst length is set to eight. The remaining (leastsignificant) address bit(s) are used to select the starting locationwithin the block. Full-page bursts wrap within the page if the boundaryis reached.

Accesses within a given burst may be programmed to be either sequentialor interleaved; this is referred to as the burst type and is selectedvia bit M3. The ordering of accesses within a burst is determined by theburst length, the burst type and the starting column address, as shownin Table 1.

TABLE 1 BURST DEFINITION Order of Accesses Within a Burst Burst StartingColumn Address Type = Type = Length A2 A1 A0 Sequential Interleaved 2 00-1 0-1 1 1-0 1-0 4 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-12-3-0-1 1 1 3-0-1-2 3-2-1-0 8 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 01 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-50 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-34-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-0-3-2 5-4-7-6-1-0-3-2 1 1 06-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0Full n = A0-A7 Cn, Cn + 1, Cn + 2 Not supported Page (location 0-255)Cn + 3, Cn + 4 256 . . . Cn-1, Cn . . .

Column Address Strobe (CAS) latency is a delay, in clock cycles, betweenthe registration of a READ command and the availability of the firstpiece of output data on the DQ connection. The latency can be set toone, two or three clocks cycles. For example, if a READ command isregistered at clock edge n, and the latency is m clocks, the data willbe available by clock edge n+m. The DQ connections will start drivingdata as a result of the clock edge one cycle earlier (n+m−1) and,provided that the relevant access times are met, the data will be validby clock edge n+m. For example, assuming that the clock cycle time issuch that all relevant access times are met, if a READ command isregistered at T0, and the latency is programmed to two clocks, the DQswill start driving after T1 and the data will be valid by T2, as shownin FIG. 3. FIG. 3 illustrates example operating frequencies at whichdifferent clock latency setting can be used. The normal operating modeis selected by setting M7 and M8 to zero, and the programmed burstlength applies to READ bursts.

The following truth tables provide more detail on the operation commandsof an embodiment of the memory of the present invention. An explanationis provided herein of the commands and follows Truth Table 2.

TRUTH TABLE 1 Interface Commands and DQM Operation NAME CS RAS CAS WE(FUNCTION) # # # # DQM ADDR DQs COMMAND H X X X X X X INHIBIT (NOP) NOOPERATION L H H H X X X (NOP) ACTIVE (Select L L H H X Bank/ X bank andRow activate row) READ (Select bank, L H L H X Bank/ X column and startCol READ burst) WRITE (Select L H L L X Bank/ Valid bank, column and Colstart WRITE) BURST L H H L X X Active TERMINATE ACTIVE L L H L X X XTERMINATE LOAD COMMAND L L L H X Com X REGISTER Code LOAD MODE L L L L XOp X REGISTER Code Write Enable/Output — — — — L — Active Enable WriteInhibit/Output — — — — H — High-Z High-Z

TRUTH TABLE 2 Flash Memory Command Sequences 1^(st) CYCLE 2nd CYCLE 3rdCYCLE Operation CMD ADDR ADDR DQ RP # CMD ADDR ADDR DQ RP # CMD ADDRADDR DQ RP # READ LCR 90H Bank X H ACTIVE Row Bank X H READ CA Bank X HDEVICE Config. READ LCR 70H X X H ACTIVE X X X H READ X X X H StatusRegister CLEAR LCR 50H X X H Status Register ERASE LCR 20H Bank X HACTIVE Row Bank X H WRITE X Bank D0H H/V_(HH) SETUP/ Confirm WRITE LCR40H Bank X H ACTIVE Row Bank X H WRITE Col Bank DIN H/V_(HH) SETUP/WRITE Protect LCR 60H Bank X H ACTIVE Row Bank X H WRITE X Bank 01HH/V_(HH) BLOCK/ Confirm Protect LCR 60H Bank X H ACTIVE X Bank X H WRITEX Bank F1H V_(HH) DEVICE/ Confirm Unprotect LCR 60H Bank X H ACTIVE XBank X H WRITE X Bank D0H H/V_(HH) BLOCKS/ Confirm ERASE LCR 30H Bank XH ACTIVE X Bank X H WRITE X Bank C0H H NVmode Register WRITE LCR A0HBank X H ACTIVE X Bank X H WRITE X Bank X H NVmode Register

The COMMAND INHIBIT function prevents new commands from being executedby the synchronous flash memory, regardless of whether the CLK signal isenabled. The synchronous flash memory is effectively deselected, butoperations already in progress are not affected.

The NO OPERATION (NOP) command is used to perform a NOP to thesynchronous flash memory that is selected (CS# is LOW). This preventsunwanted commands from being registered during idle or wait states, andoperations already in progress are not affected.

The mode register data is loaded via inputs A0-A11. The LOAD MODEREGISTER command can only be issued when all array banks are idle, and asubsequent executable command cannot be issued until a predeterminedtime delay (MRD) is met. The data in the NVMode Register 147 isautomatically loaded into the Mode Register 148 upon power-upinitialization and is the default data unless dynamically changed withthe LOAD MODE REGISTER command.

An ACTIVE command is used to open (or activate) a row in a particulararray bank for a subsequent access. The value on the BA0, BA1 inputsselects the bank, and the address provided on inputs A0-A11 selects therow. This row remains active for accesses until the next ACTIVE command,power-down or RESET.

The READ command is used to initiate a burst read access to an activerow. The value on the BA0, BA1 inputs selects the bank, and the addressprovided on inputs A0-A7 selects the starting column location. Read dataappears on the DQs subject to the logic level on the data mask (DQM)input that was present two clocks earlier. If a given DQM signal wasregistered HIGH, the corresponding DQs will be High-Z (high impedance)two clocks later; if the DQM signal was registered LOW, the DQs willprovide valid data. Thus, the DQM input can be used to mask output dataduring a read operation.

A WRITE command is used to initiate a single-location write access on anactive row. A WRITE command must be preceded by a WRITE SETUP command.The value on the BA0, BA1 inputs selects the bank, and the addressprovided on inputs A0-A7 selects a column location. Input data appearingon the DQs is written to the memory array, subject to the DQM inputlogic level appearing coincident with the data. If a given DQM signal isregistered LOW, the corresponding data will be written to memory; if theDQM signal is registered HIGH, the corresponding data inputs will beignored, and a WRITE will not be executed to that word/column location.A WRITE command with DQM HIGH is considered a NOP.

An ACTIVE TERMINATE command is not required for synchronous flashmemories, but can be provided to terminate a read in a manner similar tothe SDRAM PRECHARGE command. The ACTIVE TERMINATE command can be issuedto terminate a BURST READ in progress, and may or may not be bankspecific.

A BURST TERMINATE command is used to truncate either fixed-length orfull-page bursts. The most recently registered READ command prior to theBURST TERMINATE command will be truncated. BURST TERMINATE is not bankspecific.

The Load Command Register operation is used to initiate flash memorycontrol commands to the Command Execution Logic (CEL) 130. The CELreceives and interprets commands to the device. These commands controlthe operation of the Internal State Machine 132 and the read path (i.e.,memory array 102, ID Register 136 or Status Register 134).

Before any READ or WRITE commands can be issued to a bank within thesynchronous flash memory, a row in that bank must be “opened.” This isaccomplished via the ACTIVE command (defined by CS#, WE#, RAS#, CAS#),which selects both the bank and the row to be activated, see FIG. 4.

After opening a row (issuing an ACTIVE command), a READ or WRITE commandmay be issued to that row, subject to a time period (tRCD)specification, tRCD (MIN) should be divided by the clock period androunded up to the next whole number to determine the earliest clock edgeafter the ACTIVE command on which a READ or WRITE command can beentered. For example, a tRCD specification of 30 ns with a 90 MHZ clock(11.11 ns period) results in 2.7 clocks, which is rounded to 3. This isreflected in FIG. 5, which covers any case where 2<tRCD (MIN)/tCK≦3.(The same procedure is used to convert other specification limits fromtime units to clock cycles).

A subsequent ACTIVE command to a different row in the same bank can beissued without having to close a previous active row, provided theminimum time interval between successive ACTIVE commands to the samebank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while thefirst bank is being accessed, which results in a reduction of total rowaccess overhead. The minimum time interval between successive ACTIVEcommands to different banks is defined by a time period tRRD.

READ bursts are initiated with a READ command (defined by CS#, WE#,RAS#, CAS#), as shown in FIG. 6. The starting column and bank addressesare provided with the READ command. During READ bursts, the validdata-out element from the starting column address will be availablefollowing the CAS latency after the READ command. Each subsequentdata-out element will be valid by the next positive clock edge. Uponcompletion of a burst, assuming no other commands have been initiated,the DQs will go to a High-Z state. A full page burst will continue untilterminated. (At the end of the page, it will wrap to column 0 andcontinue.) Data from any READ burst may be truncated with a subsequentREAD command, and data from a fixed-length READ burst may be immediatelyfollowed by data from a subsequent READ command. In either case, acontinuous flow of data can be maintained. The first data element fromthe new burst follows either the last element of a completed burst, orthe last desired data element of a longer burst that is being truncated.The new READ command should be issued x cycles before the clock edge atwhich the last desired data element is valid, where x equals the CASlatency minus one. This is shown in FIG. 7 for CAS latencies of one, twoand three; data element n+3 is either the last of a burst of four, orthe last desired of a longer burst. The synchronous flash memory uses apipelined architecture and therefore does not require the 2n ruleassociated with a prefetch architecture. A READ command can be initiatedon any clock cycle following a previous READ command. Full-speed, randomread accesses within a page can be performed as shown in FIG. 8, or eachsubsequent READ may be performed to a different bank.

Data from any READ burst may be truncated with a subsequent WRITEcommand (WRITE commands must be preceded by WRITE SETUP), and data froma fixed-length READ burst may be immediately followed by data from asubsequent WRITE command (subject to bus turnaround limitations). TheWRITE may be initiated on the clock edge immediately following the last(or last desired) data element from the READ burst, provided that I/Ocontention can be avoided. In a given system design, there may be thepossibility that the device driving the input data would go Low-Z beforethe synchronous flash memory DQs go High-Z. In this case, at least asingle-cycle delay should occur between the last read data and the WRITEcommand.

The DQM input is used to avoid I/O contention as shown in FIG. 9. TheDQM signal must be asserted (HIGH) at least two clocks prior to theWRITE command (DQM latency is two clocks for output buffers) to suppressdata-out from the READ. Once the WRITE command is registered, the DQswill go High-Z (or remain High-Z) regardless of the state of the DQMsignal. The DQM signal must be de-asserted prior to the WRITE command(DQM latency is zero clocks for input buffers) to ensure that thewritten data is not masked. FIG. 9 shows the case where the clockfrequency allows for bus contention to be avoided without adding a NOPcycle.

A fixed-length or full-page READ burst can be truncated with eitherACTIVE TERMINATE (may or may not be bank specific) or BURST TERMINATE(not bank specific) commands. The ACTIVE TERMINATE or BURST TERMINATEcommand should be issued x cycles before the clock edge at which thelast desired data element is valid, where x equals the CAS latency minusone. This is shown in FIG. 10 for each possible CAS latency; dataelement n+3 is the last desired data element of a burst of four or thelast desired of a longer burst.

A single-location WRITE is initiated with a WRITE command (defined byCS#, WE#, RAS#, CAS#) as shown in FIG. 11. The starting column and bankaddresses are provided with the WRITE command. Once a WRITE command isregistered, a READ command can be executed as defined by Truth Tables 4and 5. An example is shown in FIG. 12. During a WRITE, the valid data-inis registered coincident with the WRITE command.

Unlike SDRAM, synchronous flash does not require a PRECHARGE command todeactivate the open row in a particular bank or the open rows in allbanks. The ACTIVE TERMINATE command is similar to the BURST TERMINATEcommand; however, ACTIVE TERMINATE may or may not be bank specific.Asserting input A10 HIGH during an ACTIVE TERMINATE command willterminate a BURST READ in any bank. When A10 is low during an ACTIVETERMINATE command, BA0 and BA1 will determine which bank will undergo aterminate operation. ACTIVE TERMINATE is considered a NOP for banks notaddressed by A10, BA0, BA1.

Power-down occurs if clock enable, CKE is registered LOW coincident witha NOP or COMMAND INHIBIT, when no accesses are in progress. Enteringpower-down deactivates the input and output buffers (excluding CKE)after internal state machine operations (including WRITE operations) arecompleted, for power savings while in standby.

The power-down state is exited by registering a NOP or COMMAND INHIBITand CKE HIGH at the desired clock edge (meeting tCKS). See FIG. 13 foran example power-down operation.

A clock suspend mode occurs when a column access/burst is in progressand CKE is registered LOW. In the clock suspend mode, an internal clockis deactivated, “freezing” the synchronous logic. For each positiveclock edge on which CKE is sampled LOW, the next internal positive clockedge is suspended. Any command or data present on the input pins at thetime of a suspended internal clock edge are ignored, any data present onthe DQ pins will remain driven, and burst counters are not incremented,as long as the clock is suspended (see example in FIG. 14). Clocksuspend mode is exited by registering CKE HIGH; the internal clock andrelated operation will resume on the subsequent positive clock edge.

The burst read/single write mode is a default mode in one embodiment.All WRITE commands result in the access of a single column location(burst of one), while READ commands access columns according to theprogrammed burst length and sequence. The following Truth Table 3illustrates memory operation using the CKE signal.

TRUTH TABLE 3 CKE CURRENT CKE_(n-1) CKE_(n) STATE COMMAND_(n) ACTION_(n)L L POWER- X Maintain POWER- DOWN DOWN CLOCK X Maintain CLOCK- SUSPENDSUSPEND L H POWER- COMMAND Exit POWER- DOWN INHIBIT or NOP DOWN CLOCK XExit CLOCK SUSPEND SUSPEND H L All Banks Idle COMMAND POWER-DOWN Readingor INHIBIT or NOP Entry Writing VALID CLOCK SUSPEND Entry H H See TruthTable 4

TRUTH TABLE 4 Current State Bank n - Command to Bank n CURRENT CS RASCAS WE STATE # # # # COMMAND/ACTION Any H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/ continueprevious operation Idle L L H H ACTIVE (Select and activate row) L L L HLOAD COMMAND REGISTER L L L L LOAD MODE REGISTER L L H L ACTIVETERMINATE Row Active L H L H READ (Select column and start READ burst) LH L L WRITE (Select column and start L L H L WRITE) L L L H ACTIVETERMINATE LOAD COMMAND REGISTER READ L H L H READ (Select column andstart new READ burst) L H L L WRITE (Select column and start L L H LWRITE) L H H L ACTIVE TERMINATE L L L H BURST TERMINATE LOAD COMMANDREGISTER WRITE L H L H READ (Select column and start new READ burst) L LL H LOAD COMMAND REGISTER

TRUTH TABLE 5 Current State Bank n - Command to Bank m CURRENT CS RASCAS WE STATE # # # # COMMAND/ACTION Any H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/ continueprevious operation Idle X X X X Any Command Otherwise Allowed to Bank mRow L L H H ACTIVE (Select and activate Activating, row) Active, or L HL H READ (Select column and start Active READ burst) Terminate L H L LWRITE (Select column and start L L H L WRITE L L L H ACTIVE TERMINATELOAD COMMAND REGISTER READ L L H H ACTIVE (Select and activate row) L HL H READ (Select column and start new READ burst) L H L L WRITE (Selectcolumn and start L L H L WRITE) L L L H ACTIVE TERMINATE LOAD COMMANDREGISTER WRITE L L H H ACTIVE (Select and activate row) L H L H READ(Select column and start READ burst) L L H L ACTIVE TERMINATE L H H LBURST TERMINATE L L L H LOAD COMMAND REGISTER

Function Description

The synchronous flash memory incorporates a number of features to makeit ideally suited for code storage and execute-in-place applications onan SDRAM bus. The memory array is segmented into individual eraseblocks. Each block may be erased without affecting data stored in otherblocks. These memory blocks are read, written and erased by issuingcommands to the command execution logic 130 (CEL). The CEL controls theoperation of the Internal State Machine 132 (ISM), which completelycontrols all ERASE NVMODE REGISTER, WRITE NVMODE REGISTER, WRITE, BLOCKERASE, BLOCK PROTECT, DEVICE PROTECT, UNPROTECT ALL BLOCKS and VERIFYoperations. The ISM 132 protects each memory location from over-erasureand optimizes each memory location for maximum data retention. Inaddition, the ISM greatly simplifies the control necessary for writingthe device in-system or in an external programmer.

The synchronous flash memory is organized into 16 independently erasablememory blocks that allow portions of the memory to be erased withoutaffecting the rest of the memory data. Any block may behardware-protected against inadvertent erasure or writes. A protectedblock requires that the RP# pin be driven to VHH (a relatively highvoltage) before being modified. The 256K-word blocks at locations 0 and15 can have additional hardware protection. Once a PROTECT BLOCK commandhas been executed to these blocks, an UNPROTECT ALL BLOCKS command willunlock all blocks except the blocks at locations 0 and 15, unless theRP# pin is at VHH. This provides additional security for critical codeduring in-system firmware updates, should an unintentional powerdisruption or system reset occur.

Power-up initialization, ERASE, WRITE and PROTECT timings are simplifiedby using an ISM to control all programming algorithms in the memoryarray. The ISM ensures protection against over-erasure and optimizeswrite margin to each cell. During WRITE operations, the ISMautomatically increments and monitors WRITE attempts, verifies writemargin on each memory cell and updates the ISM Status Register. When aBLOCK ERASE operation is performed, the ISM automatically overwrites theentire addressed block (eliminates over-erasure), increments andmonitors ERASE attempts and sets bits in the ISM Status Register.

The 8-bit ISM Status Register 134 allows an external processor 200 tomonitor the status of the ISM during WRITE, ERASE and PROTECToperations. One bit of the 8-bit Status Register (SR7) is set andcleared entirely by the ISM. This bit indicates whether the ISM is busywith an ERASE, WRITE or PROTECT task. Additional error information isset in three other bits (SR3, SR4 and SR5): write and protect blockerror, erase and unprotect all blocks error, and device protectionerror. Status register bits SR0, SR1 and SR2 provide details on the ISMoperation underway. The user can monitor whether a device-level orbank-level ISM operation (including which bank is under ISM control) isunderway. These six bits (SR3-SR5) must be cleared by the host system.The status register is described in further detail below with referenceto Table 2.

The CEL 130 receives and interprets commands to the device. Thesecommands control the operation of the ISM and the read path (i.e.,memory array, device configuration or status register). Commands may beissued to the CEL while the ISM is active.

To allow for maximum power conservation, the synchronous flash featuresa very low current, deep power-down mode. To enter this mode, the RP#pin 140 (reset/power-down) is taken to VSS±0.2V. To prevent aninadvertent RESET, RP# must be held at Vss for 100 ns prior to thedevice entering the reset mode. With RP# held at Vss, the device willenter the deep power-down mode. After the device enters the deeppower-down mode, a transition from LOW to HIGH on RP# will result in adevice power-up initialize sequence as outlined herein. TransitioningRP# from LOW to HIGH after entering the reset mode but prior to enteringdeep power-down mode requires a 1 μs delay prior to issuing anexecutable command. When the device enters the deep power-down mode, allbuffers excluding the RP# buffer are disabled and the current draw islow, for example, a maximum of 50 μA at 3.3V VCC. The input to RP# mustremain at Vss during deep power-down. Entering the RESET mode clears theStatus Register 134 and sets the ISM 132 to the array read mode.

The synchronous flash memory array architecture is designed to allowsectors to be erased without disturbing the rest of the array. The arrayis divided into 16 addressable “blocks” that are independently erasable.By erasing blocks rather than the entire array, the total deviceendurance is enhanced, as is system flexibility. Only the ERASE andBLOCK PROTECT functions are block oriented. The 16 addressable blocksare equally divided into four banks 104, 106, 108 and 110 of four blockseach. The four banks have simultaneous read-while-write functionality.An ISM WRITE or ERASE operation to any bank can occur simultaneously toa READ operation to any other bank. The Status Register 134 may bepolled to determine which bank is under ISM operation. The synchronousflash memory has a single background operation ISM to control power-upinitialization, ERASE, WRITE, and PROTECT operations. Only one ISMoperation can occur at any time; however, certain other commands,including READ operations, can be performed while the ISM operation istaking place. An operational command controlled by the ISM is defined aseither a bank-level operation or a device-level operation. WRITE andERASE are bank-level ISM operations. After an ISM bank operation hasbeen initiated, a READ to any location in the bank may output invaliddata, whereas a READ to any other bank will read the array. A READSTATUS REGISTER command will output the contents of the Status Register134. The ISM status bit will indicate when the ISM operation is complete(SR7=1). When the ISM operation is complete, the bank will automaticallyenter the array read mode. ERASE NVMODE REGISTER, WRITE NVMODE REGISTER,BLOCK PROTECT, DEVICE PROTECT, and UNPROTECT ALL BLOCKS are device-levelISM operations. Once an ISM device-level operation has been initiated, aREAD to any bank will output the contents of the array. A READ STATUSREGISTER command may be issued to determine completion of the ISMoperation. When SR7=1, the ISM operation will be complete and asubsequent ISM operation may be initiated. Any block may be protectedfrom unintentional ERASE or WRITE with a hardware circuit that requiresthe RP# pin be driven to VHH before a WRITE or ERASE is commenced, asexplained below.

Any block may be hardware-protected to provide extra security for themost sensitive portions of the firmware. During a WRITE or ERASE of ahardware protected block, the RP# pin must be held at VHH until theWRITE or ERASE is completed. Any WRITE or ERASE attempt on a protectedblock without RP#=VHH will be prevented and will result in a write orerase error. The blocks at locations 0 and 15 can have additionalhardware protection to prevent an inadvertent WRITE or ERASE operation.In this embodiment, these blocks cannot be software-unlocked through anUNPROTECT ALL BLOCKS command unless RP#=VHH. The protection status ofany block may be checked by reading its block protect bit with a READSTATUS REGISTER command.

Further, to protect a block, a three-cycle command sequence must beissued with the block address.

The synchronous flash memory can feature three different types of READs.Depending on the mode, a READ operation will produce data from thememory array, status register, or one of the device configurationregisters. A READ to the device configuration register or the StatusRegister must be preceded by an LCR-ACTIVE cycle and burst length ofdata out will be defined by the mode register settings. A subsequentREAD or a READ not preceded by an LCR-ACTIVE cycle will read the array.However, several differences exist and are described in the followingsection.

A READ command to any bank outputs the contents of the memory array.While a WRITE or ERASE ISM operation is taking place, a READ to anylocation in the bank under ISM control may output invalid data. Uponexiting a RESET operation, the device will automatically enter the arrayread mode.

Performing a READ of the Status Register 134 requires the same inputsequencing as when reading the array, except that an LCR READ STATUSREGISTER (70H) cycle must precede the ACTIVE READ cycles. The burstlength of the Status Register data-out is defined by the Mode Register148. The Status Register contents are updated and latched on the nextpositive clock edge subject to CAS latencies. The device willautomatically enter the array read mode for subsequent READs.

Reading any of the Device Configuration Registers 136 requires the sameinput sequencing as when reading the Status Register except thatspecific addresses must be issued. WE# must be HIGH, and DQM and CS#must be LOW. To read the manufacturer compatibility ID, addresses mustbe at 000000H, and to read the device ID, addresses must be at 000001H.Any of the block protect bits is read at the third address locationwithin each erase block (xx0002H), while the device protect bit is readfrom location 000003H.

The DQ pins are used either to input data to the array. The address pinsare used either to specify an address location or to input a command tothe CEL during the LOAD COMMAND REGISTER cycle. A command input issuesan 8-bit command to the CEL to control the operation mode of the device.A WRITE is used to input data to the memory array. The following sectiondescribes both types of inputs.

To perform a command input, DQM must be LOW, and CS# and WE# must beLOW. Address pins or DQ pins are used to input commands. Address pinsnot used for input commands are “Don't Care” and must be held stable.The 8-bit command is input on DQ0-DQ7 or A0-A7 and is latched on thepositive clock edge.

A WRITE to the memory array sets the desired bits to logic 0s but cannotchange a given bit to a logic 1 from a logic 0. Setting any bits to alogic 1 requires that the entire block be erased. To perform a WRITE,DQM must be LOW, CS# and WE# must be LOW, and VCCP must be tied to VCC.Writing to a protected block also requires that the RP# pin be broughtto VHH. A0-A11 provide the address to be written, while the data to bewritten to the array is input on the DQ pins. The data and addresses arelatched on the rising edge of the clock. A WRITE must be preceded by aWRITE SETUP command.

To simplify the writing of the memory blocks, the synchronous flashincorporates an ISM that controls all internal algorithms for the WRITEand ERASE cycles. An 8-bit command set is used to control the device.See Truth Tables 1 and 2 for a list of the valid commands.

The 8-bit ISM Status Register 134 (see Table 2) is polled to check forERASE NVMODE REGISTER, WRITE NVMODE REGISTER, WRITE, ERASE, BLOCKPROTECT, DEVICE PROTECT or UNPROTECT ALL BLOCKS completion or anyrelated errors. Completion of an ISM operation can be monitored byissuing a READ STATUS REGISTER (70H) command. The contents of the StatusRegister will be output to DQ0-DQ7 and updated on the next positiveclock edge (subject to CAS latencies) for a fixed burst length asdefined by the mode register settings. The ISM operation will becomplete when SR7=1. All of the defined bits are set by the ISM, butonly the ISM status bit is reset by the ISM. The erase/unprotect block,write/protect block, device protection must be cleared using a CLEARSTATUS REGISTER (50H) command. This allows the user to choose when topoll and clear the Status Register. For example, a host system mayperform multiple WRITE operations before checking the Status Registerinstead of checking after each individual WRITE. Asserting the RP#signal or powering down the device will also clear the Status Register.

TABLE 2 STATUS REGISTER STATUS BIT# STATUS REGISTER BIT DESCRIPTION SR7ISM STATUS The ISMS bit displays the active 1 = Ready status of thestate machine when 0 = Busy performing WRITE or BLOCK ERASE. Thecontrolling logic polls this bit to determine when the erase and writestatus bits are valid. SR6 RESERVE Reserved for future use. SR5ERASE/UNPROTECT BLOCK ES is set to 1 after the maximum STATUS number ofERASE cycles is 1 = BLOCK ERASE or executed by the ISM without a BLOCKUNPROTECT error successful verify. This bit is also set 0 = SuccessfulBLOCK ERASE to 1 if a BLOCK UNPROTECT or UNPROTECT operation isunsuccessful. ES is only cleared by a CLEAR STATUS REGISTER command orby a RESET. SR4 WRITE/PROTECT BLOCK WS is set to 1 after the maximumSTATUS number of WRITE cycles is 1 = WRITE or BLOCK executed by the ISMwithout a PROTECT error successful verify. This bit is also set 0 =Successful WRITE or to 1 if a BLOCK or DEVICE BLOCK PROTECT PROTECToperation is unsuccessful. WS is only cleared by a CLEAR STATUS REGISTERcommand or by a RESET. SR2 BANKA1 ISM STATUS When SR0 = 0, the bankunder ISM SR1 BANKA0 ISM STATUS control can be decoded from BA0, BA1:[0,0] Bank0; [0,1] Bank1; [1,0] Bank2; [1,1] Bank3. SR3 DEVICE PROTECTSTATUS DPS is set to 1 if an invalid WRITE, 1 = Device protected,invalid ERASE, PROTECT BLOCK, operation attempted PROTECT DEVICE or 0 =Device unprotected or RP# UNPROTECT ALL BLOCKS is condition metattempted. After one of these commands is issued, the condition of RP#,the block protect bit and the device protect bit are compared todetermine if the desired operation is allowed. Must be cleared by CLEARSTATUS REGISTER or by a RESET. SR0 DEVICE/BANK ISM STATUS DBS is set to1 if the ISM operation 1 = Device level ISM operation is a device-leveloperation. A valid 0 = Bank level ISM operation READ to any bank of thearray can immediately follow the registration of a device-level ISMWRITE operation. When DBS is set to 0, the ISM operation is a bank-leveloperation. A READ to the bank under ISM control may result in invaliddata. SR2 and SR3 can be decoded to determine which bank is under ISMcontrol.

The device ID, manufacturer compatibility ID, device protection statusand block protect status can all be read by issuing a READ DEVICECONFIGURATION (90H) command. To read the desired register, a specificaddress must be asserted. See Table 3 for more details on the variousdevice configuration registers 136.

TABLE 3 DEVICE CONFIGURATION DEVICE CONFIGURATION ADDRESS DATA CONDITIONManufacturer 000000H 2CH Manufacturer Compatibility compatibility readDevice ID 000001H D3H Device ID read Block Protect Bit xx0002H DQ0 = 1Block protected DQ0 = 0 Block unprotected xx0002H Device Protect Bit000003H DQ0 = 1 Block protect DQ0 = 0 modification prevented 000003HBlock protect modification enabled

Commands can be issued to bring the device into different operationalmodes. Each mode has specific operations that can be performed while inthat mode. Several modes require a sequence of commands to be writtenbefore they are reached. The following section describes the propertiesof each mode, and Truth Tables 1 and 2 list all command sequencesrequired to perform the desired operation. Read-while-writefunctionality allows a background operation write or erase to beperformed on any bank while simultaneously reading any other bank. For awrite operation, the LCR-ACTIVE-WRITE command sequences in Truth Table 2must be completed on consecutive clock cycles. However, to simplify asynchronous flash controller operation, an unlimited number of NOPs orCOMMAND INHIBITs can be issued throughout the command sequence. Foradditional protection, these command sequences must have the same bankaddress for the three cycles. If the bank address changes during theLCR-ACTIVE-WRITE command sequence, or if the command sequences are notconsecutive (other than NOPs and COMMAND INHIBITs, which are permitted),the write and erase status bits (SR4 and SR5) will be set and theoperation prohibited.

Upon power-up and prior to issuing any operational commands to thedevice, the synchronous flash is initialized. After power is applied toVCC, VCCQ and VCCP (simultaneously), and the clock is stable, RP# istransitioned from LOW to HIGH. A delay (in one embodiment a 100 μsdelay) is required after RP# transitions HIGH in order to completeinternal device initialization. The device is in the array read mode atthe completion of device initialization, and an executable command canbe issued to the device.

To read the device ID, manufacturer compatibility ID, device protect bitand each of the block protect bits, a READ DEVICE CONFIGURATION (90H)command is issued. While in this mode, specific addresses are issued toread the desired information. The manufacturer compatibility ID is readat 000000H; the device ID is read at 000001H. The manufacturercompatibility ID and device ID are output on DQ0-DQ7. The device protectbit is read at 000003H; and each of the block protect bits is read atthe third address location within each block xx0002H). The device andblock protect bits are output on DQ0.

Three consecutive commands on consecutive clock edges are needed toinput data to the array (NOPs and Command Inhibits are permitted betweencycles). In the first cycle, a LOAD COMMAND REGISTER command is givenwith WRITE SETUP (40H) on A0-A7, and the bank address is issued on BA0,BA1. The next command is ACTIVE, which activates the row address andconfirms the bank address. The third cycle is WRITE, during which thestarting column, the bank address, and data are issued. The ISM statusbit will be set on the following clock edge (subject to CAS latencies).While the ISM executes the WRITE, the ISM status bit (SR7) will be at 0.A READ operation to the bank under ISM control may produce invalid data.When the ISM status bit (SR7) is set to a logic 1, the WRITE has beencompleted, and the bank will be in the array read mode and ready for anexecutable command. Writing to hardware-protected blocks also requiresthat the RP# pin be set to VHH prior to the third cycle (WRITE), and RP#must be held at VHH until the ISM WRITE operation is complete. The writeand erase status bits (SR4 and SR5) will be set if the LCR-ACTIVE-WRITEcommand sequence is not completed on consecutive cycles or the bankaddress changes for any of the three cycles. After the ISM has initiatedthe WRITE, it cannot be aborted except by a RESET or by powering downthe part. Doing either during a WRITE may corrupt the data beingwritten.

Executing an ERASE sequence will set all bits within a block to logic 1.The command sequence necessary to execute an ERASE is similar to that ofa WRITE. To provide added security against accidental block erasure,three consecutive command sequences on consecutive clock edges arerequired to initiate an ERASE of a block. In the first cycle, LOADCOMMAND REGISTER is given with ERASE SETUP (20H) on A0-A7, and the bankaddress of the block to be erased is issued on BA0, BA1. The nextcommand is ACTIVE, where A10, A11, BA0, BA1 provide the address of theblock to be erased. The third cycle is WRITE, during which ERASE CONFRIM(DOH) is given on DQ0-DQ7 and the bank address is reissued. The ISMstatus bit will be set on the following clock edge (subject to CASlatencies). After ERASE CONFIRM (D0H) is issued, the ISM will start theERASE of the addressed block. Any READ operation to the bank where theaddressed block resides may output invalid data. When the ERASEoperation is complete, the bank will be in the array read mode and readyfor an executable command. Erasing hardware-protected blocks alsorequires that the RP# pin be set to VHH prior to the third cycle(WRITE), and RP# must be held at VHH until the ERASE is completed(SR7=1). If the LCR-ACTIVE-WRITE command sequence is not completed onconsecutive cycles (NOPs and COMMAND INHIBITs are permitted betweencycles) or the bank address changes for one or more of the commandcycles, the write and erase status bits (SR4 and SR5) will be set andthe operation is prohibited.

The contents of the Mode Register 148 may be copied into the NVModeRegister 147 with a WRITE NVMODE REGISTER command. Prior to writing tothe NVMode Register, an ERASE NVMODE REGISTER command sequence must becompleted to set all bits in the NVMode Register to logic 1. The commandsequence necessary to execute an ERASE NVMODE REGISTER and WRITE NVMODEREGISTER is similar to that of a WRITE. See Truth Table 2 for moreinformation on the LCR-ACTIVE-WRITE commands necessary to complete ERASENVMODE REGISTER and WRITE NVMODE REGISTER. After the WRITE cycle of theERASE NVMODE REGISTER or WRITE NVMODE REGISTER command sequence has beenregistered, a READ command may be issued to the array. A new WRITEoperation will not be permitted until the current ISM operation iscomplete and SR7=1.

Executing a BLOCK PROTECT sequence enables the first level ofsoftware/hardware protection for a given block. The memory includes a16-bit register that has one bit corresponding to the 16 protectableblocks. The memory also has a register to provide a device bit used toprotect the entire device from write and erase operations. The commandsequence necessary to execute a BLOCK PROTECT is similar to that of aWRITE. To provide added security against accidental block protection,three consecutive command cycles are required to initiate a BLOCKPROTECT. In the first cycle, a LOAD COMMAND REGISTER is issued with aPROTECT SETUP (60H) command on A0-A7, and the bank address of the blockto be protected is issued on BA0, BA1. The next command is ACTIVE, whichactivates a row in the block to be protected and confirms the bankaddress. The third cycle is WRITE, during which BLOCK PROTECT CONFIRM(01H) is issued on DQ0-DQ7, and the bank address is reissued. The ISMstatus bit will be set on the following clock edge (subject to CASlatencies). The ISM will then begin the PROTECT operation. If theLCR-ACTIVE-WRITE is not completed on consecutive cycles (NOPs andCOMMAND INHIBITs are permitted between cycles) or the bank addresschanges, the write and erase status bits (SR4 and SR5) will be set andthe operation is prohibited. When the ISM status bit (SR7) is set to alogic 1, the PROTECT has been completed, and the bank will be in thearray read mode and ready for an executable command. Once a blockprotect bit has been set to a 1 (protected), it can only be reset to a 0if the UNPROTECT ALL BLOCKS command. The UNPROTECT ALL BLOCKS commandsequence is similar to the BLOCK PROTECT command; however, in the thirdcycle, a WRITE is issued with a UNPROTECT ALL BLOCKS CONFIRM (D0H)command and addresses are “Don't Care.” For additional information,refer to Truth Table 2. The blocks at locations 0 and 15 have additionalsecurity. Once the block protect bits at locations 0 and 15 have beenset to a 1 (protected), each bit can only be reset to a 0 if RP# isbrought to VHH prior to the third cycle of the UNPROTECT operation, andheld at VHH until the operation is complete (SR7=1). Further, if thedevice protect bit is set, RP# must be brought to VHH prior to the thirdcycle and held at VHH until the BLOCK PROTECT or UNPROTECT ALL BLOCKSoperation is complete. To check a block's protect status, a READ DEVICECON FIGURATION (90H) command may be issued.

Executing a DEVICE PROTECT sequence sets the device protect bit to a 1and prevents a block protect bit modification. The command sequencenecessary to execute a DEVICE PROTECT is similar to that of a WRITE.Three consecutive command cycles are required to initiate a DEVICEPROTECT sequence. In the first cycle, LOAD COMMAND REGISTER is issuedwith a PROTECT SETUP (60H) on A0-A7, and a bank address is issued onBA0, BA1. The bank address is “Don't Care” but the same bank addressmust be used for all three cycles. The next command is ACTIVE. The thirdcycle is WRITE, during which a DEVICE PROTECT (F1H) command is issued onDQ0-DQ7, and RP# is brought to VHH. The ISM status bit will be set onthe following clock edge (subject to CAS latencies). An executablecommand can be issued to the device. RP# must be held at VHH until theWRITE is completed (SR7=1). A new WRITE operation will not be permitteduntil the current ISM operation is complete. Once the device protect bitis set, it cannot be reset to a 0. With the device protect bit set to a1, BLOCK PROTECT or BLOCK UNPROTECT is prevented unless RP# is at VHHduring either operation. The device protect bit does not affect WRITE orERASE operations. Refer to Table 4 for more information on block anddevice protect operations.

TABLE 4 PROTECT OPERATIONS TRUTH TABLE FUNCTION RP # CS # DQM WE #Address VccP DQ0-DQ7 DEVICE UNPROTECTED PROTECT SETUP H L H L 60H X XPROTECT BLOCK H L H L BA H 01H PROTECT DEVICE V_(HH) L H L X X F1HUNPROTECT ALL H/V_(HH) L H L X H D0H BLOCKS DEVICE PROTECTED PROTECTSETUP H or L H L 60H X X V_(HH) PROTECT BLOCK V_(HH) L H L BA H 01HUNPROTECT ALL V_(HH) L H L X H D0H BLOCKS

After the ISM status bit (SR7) has been set, the device/bank (SR0),device protect (SR3), bankA0 (SR1), bankA1 (SR2), write/protect block(SR4) and erase/unprotect (SR5) status bits may be checked. If one or acombination of SR3, SR4, SR5 status bits has been set, an error hasoccurred during operation. The ISM cannot reset the SR3, SR4 or SR5bits. To clear these bits, a CLEAR STATUS REGISTER (50H) command must begiven. Table 5 lists the combinations of errors.

TABLE 5 STATUS REGISTER ERROR DECODE STATUS BITS SR5 SR4 SR3 ERRORDESCRIPTION 0 0 0 No errors 0 1 0 WRITE, BLOCK PROTECT or DEVICE PROTECTerror 0 1 1 Invalid BLOCK PROTECT or DEVICE PROTECT, RP# not valid(V_(HH)) 0 1 1 Invalid BLOCK or DEVICE PROTECT, RP# not valid 1 0 0ERASE or ALL BLOCK UNPROTECT error 1 0 1 Invalid ALL BLOCK UNPROTECT,RP# not valid (V_(HH)) 1 1 0 Command sequencing error

The synchronous flash memory is designed and fabricated to meet advancedcode and data storage requirements. To ensure this level of reliability,VCCP must be tied to Vcc during WRITE or ERASE cycles. Operation outsidethese limits may reduced the number of WRITE and ERASE cycles that canbe performed on the device. Each block is designed and processed for aminimum of 100,000-WRITE/ERASE-cycle endurance.

The synchronous flash memory offers several power-saving features thatmay be utilized in the array read mode to conserve power. A deeppower-down mode is enabled by bringing RP# to VSS±0.2V. Current draw(ICC) in this mode is low, such as a maximum of 50 μA. When CS# is HIGH,the device will enter the active standby mode. In this mode the currentis also low, such as a maximum ICC current of 30 mA. If CS# is broughtHIGH during a write, erase, or protect operation, the ISM will continuethe WRITE operation, and the device will consume active Iccp power untilthe operation is completed.

Referring to FIG. 16, a flow chart of a self-timed write sequenceaccording to one embodiment of the present invention is described. Thesequence includes loading the command register (code 40H), receiving anactive command and a row address, and receiving a write command and acolumn address. The sequence then provides for a status register pollingto determine if the write is complete. The polling monitors statusregister bit 7 (SR7) to determine if it is set to a 1. An optionalstatus check can be included. When the write is completed, the array isplaced in the array read mode.

Referring to FIG. 17, a flow chart of a complete write status-checksequence according to one embodiment of the present invention isprovided. The sequence looks for status register bit 4 (SR4) todetermine if it is set to a 0. If SR4 is a 1, there was an error in thewrite operation. The sequence also looks for status register bit 3 (SR3) to determine if it is set to a 0. If SR3 is a 1, there was an invalidwrite error during the write operation.

Referring to FIG. 18, a flow chart of a self-timed block erase sequenceaccording to one embodiment of the present invention is provided. Thesequence includes loading the command register (code 20H), and receivingan active command and a row address. The memory then determines if theblock is protected. If it is not protected, the memory performs a writeoperation (D0H) to the block and monitors the status register forcompletion. An optional status check can be performed and the memory isplaced in an array read mode. If the block is protected, the erase isnot allowed unless the RP# signal is at an elevated voltage (VHH).

FIG. 19 illustrates a flow chart of a complete block erase status-checksequence according to one embodiment of the present invention. Thesequence monitors the status register to determine if a command sequenceerror occurred (SR4 or SR5=1). If SR3 is set to a 1, an invalid erase orunprotect error occurred. Finally, a block erase or unprotect errorhappened if SR5 is set to a 1.

FIG. 20 is a flow chart of a block protect sequence according to oneembodiment of the present invention. The sequence includes loading thecommand register (code 60H), and receiving an active command and a rowaddress. The memory then determines if the block is protected. If it isnot protected, the memory performs a write operation (01H) to the blockand monitors the status register for completion. An optional statuscheck can be performed and the memory is placed in an array read mode.If the block is protected, the erase is not allowed unless the RP#signal is at an elevated voltage (VHH).

Referring to FIG. 21, a flow chart of a complete block status-checksequence according to one embodiment of the present invention isprovided. The sequence monitors the status register bits 3, 4 and 5 todetermine of errors were detected.

FIG. 22 is a flow chart of a device protect sequence according to oneembodiment of the present invention. The sequence includes loading thecommand register (code 60H), and receiving an active command and a rowaddress. The memory then determines if RP# is at VHH. The memoryperforms a write operation (F1H) and monitors the status register forcompletion. An optional status check can be performed and the memory isplaced in an array read mode.

FIG. 23 is a flow chart of a block unprotect sequence according to oneembodiment of the present invention. The sequence includes loading thecommand register (code 60H), and receiving an active command and a rowaddress. The memory then determines if the memory device is protected.If it is not protected, the memory determines if the boot locations(blocks 0 and 15) are protected. If none of the blocks are protected thememory performs a write operation (D0H) to the block and monitors thestatus register for completion. An optional status check can beperformed and the memory is placed in an array read mode. If the deviceis protected, the erase is not allowed unless the RP# signal is at anelevated voltage (VHH). Likewise, if the boot locations are protected,the memory determines if all blocks should be unprotected.

FIG. 24 illustrates the timing of an initialize and load mode registeroperation. The mode register is programmed by providing a load moderegister command and providing operation code (opcode) on the addresslines. The opcode is loaded into the mode register. As explained above,the contents of the non-volatile mode register are automatically loadedinto the mode register upon power-up and the load mode registeroperation may not be needed.

FIG. 25 illustrates the timing of a clock suspend mode operation, andFIG. 26 illustrates the timing of another burst read operation. FIG. 27illustrates the timing of alternating bank read accesses. Here activecommand are needed to change bank addresses. A full page burst readoperation is illustrated in FIG. 28. Note that the full page burst doesnot self terminate, but requires a terminate command.

FIG. 29 illustrates the timing of a read operation using a data masksignal. The DQM signal is used to mask the data output so that Dout m+1is not provided on the DQ connections.

Referring to FIG. 30, the timing of a write operation followed by a readto a different bank is illustrated. In this operation, a write isperformed to bank a and a subsequent read is performed to bank b. Thesame row is accessed in each bank.

Referring to FIG. 31, the timing of a write operation followed by a readto the same bank is illustrated. In this operation, a write is performedto bank a and a subsequent read is performed to bank a. A different rowis accessed for the read operation, and the memory must wait for theprior write operation to be completed. This is different from the readof FIG. 30 where the read was not delayed due to the write operation.

The synchronous Flash memory provides for a latency free writeoperation. This is different from a SDRAM that requires the system toprovide latency for write operations, just like a read operation. So thewrite operation does not take away from the system bus as many cycles asthe SDRAM takes, and hence can improve the system read throughput, seeFIG. 12 where the write data, Din, is provided on the same clock cycleas the write command and column address. The clock cycle, T1, of FIG. 12does not need to be a NOP command (see FIG. 30). The read command can beprovided on the next clock cycle following the write data. Thus, whilethe read operation requires that the DQ connections remain available fora predetermined number of clock cycles following the read command(latency), the DQ connections can be used immediately after the writecommand is provided (no latency). As such, the present invention allowsfor zero bus turn around capability. This is substantially differentfrom the SDRAM, where multiple waits are required on the system bus whengoing between read and write operations. The synchronous flash providesthese two features, and could improve bus throughput.

Referring to FIG. 32, a system 300 of the present invention includes asynchronous memory 302 that has internal write latches 304 that are usedto store write data received on the DQ inputs 306. The write latches arecoupled to the memory array 310. Again, the memory array can be arrangedin a number of addressable blocks. Data can be written to one blockwhile a read operation can be performed on the other blocks. The memorycells of the array can be non-volatile memory cells. Data communicationconnections 306 are used for bi-directional data communication with anexternal device, such as a processor 320 or other memory controller.

data buffer 330 can be coupled to the data communication connections tomanage the bi-directional data communication. This buffer can be atraditional FIFO or pipelined input/output buffer circuit. The writelatch is coupled between the data buffer and the memory array to latchdata provided on the data communication connections. Finally, a controlcircuit is provided to manage the read and write operations performed onthe array.

By latching the input write data, the data bus 306 (DQ's) can bereleased and the write operation performed using the latched data.Subsequent write operations to the memory can be prohibited while thefirst write operation is being performed. The bus, however, is availableto immediately perform a read operation on the memory.

The present invention should not be confused with traditionalinput/output buffer architecture. That is, while prior memory devicesused an input buffer on the DQ input path and an output buffer on the DQoutput path, the clock latency used for both read and write operationsare maintained the same. The present invention can include input/outputbuffer circuitry to provide an interface with the DQ connections and anexternal processor. The additional write latches allow the memory toisolate the write path/operation to one area of the memory whileallowing data read operations on other memory areas.

Prior flash memory devices have had very limited concurrent operationcapabilities. That is, prior flash memories typically blocked readingfrom the memory while a write operation was performed. Some memorydevices allowed reading while writing by suspending an ongoing writeoperation, then allowing the reading of the array. Yet other flashmemories allow for read-while-write by providing a limited sector thatcan be written while the remainder of the memory is available forreading. The intention of such flash memories has been to eliminate theneed for a separate EEPROM in a system. The limited sector spaceprovides an EEPROM location in the flash and leaves the rest of memoryfor the flash operation.

The present invention provides a flash array that is arranged into bankstructures similar to an SDRAM. In one embodiment, a 64M synchronousflash is divided into four banks with the same addressing as a 64MSDRAM. Those banks are further broken into smaller addressable sectorsthat can be erased or programmed. The memory allows concurrent readingand writing on a per bank basis. Thus, one bank can be written while aconcurrent read can be executed on any of the other banks.

As known to one skilled in the art, an SDRAM can have one common rowopen in each bank. Read and write operations can be performedsequentially over the open row and across the array banks.

The present synchronous flash memory has a bank architecture similar toSDRAM that allows a row to be opened in each of the banks while one ofthe banks is being written to. Referring to FIG. 33, one embodiment of aprocessing system 400 of the present invention is illustrated. Asynchronous flash memory 410 is coupled to multiple processors 440, 442,444 and 446 via a bi-directional data bus 435. The memory includes anarray of non-volatile memory cells arranged in multiple banks 412, 414,416 and 418. Read/write circuitry 430 is generally illustrated to managethe data communication with the array. In operation, a processor, suchas processor 440, can initiate a write operation on row 420 of arraybank 412. While the write operation is being performed, a secondprocessor, such as processor 442, can read data from row 420 of a secondarray bank. This allows four processors to be independently working onthe synchronous flash memory device. The present invention is notlimited to four banks or four processors. Single or multiple processorscan perform a write operation on one bank while reading data from theremaining memory array banks, see for example FIG. 32. Thus, there canbe concurrent write and multiple concurrent read operations ongoing.

Multiple Status Reading Capabilities

As explained above, the synchronous flash of the present invention canperform a bank specific read operation while concurrently performing awrite operation on another bank. A problem can be experienced when firstand second external processors try reading and writing to the memory.That is, the two processors need to know what operations are beingperformed on the memory to avoid contention if the processors attempt toperform operations on the same memory block. In prior systems, a busmaster is used to keep track of concurrent operations performed bymultiple processors. Two options are available to reduce the overhead ofa bus master.

One option is to include an automatic read status mode in the memorythat outputs the contents of the status register when a second operationis attempted on the memory. That is, when a write is being performed onthe memory, any read operation performed on the memory outputs thecontents of the status register. This option interrupts the readoperation by outputting the status data, even if the read operation wereattempted on a different array block. A second option is to require theprocessor to read the status register to determine a write status of thememory. Again, the read operation is interrupted with this option.

The present invention can provide two status reading modes to avoiddisruptions in concurrent read operations to a different array bank. Afirst status mode provided in the present synchronous flash memoryprovides a status of the entire memory device. That is, the statusregister indicates if a write operation is being performed on a memoryarray or a non-array register. This status mode, referred to herein asmemory status mode, is selectively activated by a request from anexternal processor. In response to a memory status command, the controlcircuitry of the memory provides the status register data on the DQconnections.

The second status mode is a memory array bank specific mode. In thismode, status data is automatically provided on the DQ connections. Thatis, if a processor initiates a write operation to an array bank, thebank is placed in a bank status mode. Any subsequent attempts to readfrom that bank while the write operation is being performed results inan output of the status register data on the DQ connections. Thus, thememory control circuitry allows multi-processor systems to work togetherwithout interfering with each other.

The memory includes a multi-bit bank register 450 (FIG. 33) that can beset to identify which array bank is being written. In operation, thememory programs the bank register and uses the bank register as apointer. During a read operation, a read address is compared to the bankregister, and the memory automatically outputs the status register dataif there is an ongoing write operation at that bank address. The presentinvention, therefore, may reduce overhead of a bus master and hence mayallow for better multi processing capabilities.

CONCLUSION

synchronous flash memory includes an array of non-volatile memory cells.The memory array is arranged in rows and columns, and can be furtherarranged in addressable blocks. Data communication connections are usedfor bi-directional data communication with an external device(s), suchas a processor or other memory controller. A write latch is coupledbetween the data buffer and the memory array to latch data provided onthe data communication connections. The memory can write data to onelocation, such as a memory array block, while data is read from a secondlocation, such as a second memory array block. The memory automaticallyprovides status data when a read command is received for a memory arraylocation that is currently subject to a write operation. The automaticstatus output allows multiple processors to access the memory devicewithout substantial bus master overhead. The memory can also outputstatus data in response to a status read command.

What is claimed is:
 1. A processing system comprising; a firstprocessor; a second processor; and a synchronous memory device coupledto the first and second processors, the synchronous memory devicecomprising, an array of memory cells arranged in a plurality ofaddressable blocks, a bank register having a plurality of bitscorresponding to the plurality of blocks, an array status register tostore status data indicating where a write operation is performed on thearray, control circuitry to perform a write operation on a first blockof the plurality of blocks in response to a write command from the firstprocessor, and automatically couple the status data to external dataconnections in response to a read command from the second processor. 2.The processing system of claim 1 wherein the synchronous memory devicefurther comprises: a plurality of non-volatile programmable registers;and a memory status register to store memory write status dataindicating if data is being written to the array of one of the pluralityof non-volatile programmable registers, and wherein the controlcircuitry outputs the memory write status data in response to anexternally provided status request command from the second processor. 3.A processing system, comprising: a first processor; a second processor;and a memory device coupled to the first and second processors, thememory device comprising: an array of memory cells arranged in aplurality of addressable blocks; and memory status circuitry to output amemory status signal in response to a request for a read operation onthe array.
 4. The processing system of claim 3, wherein the memorystatus circuitry comprises: a memory status register to store memorywrite status data indicating if data is being written to the array ofone of the plurality of non-volatile programmable registers; and controlcircuitry to provide the memory write status data in response to amemory status command.
 5. The processing system of claim 4, and furthercomprising: array status circuitry to automatically couple status dataof a block of the array to external data connections in response to aread command on the block.
 6. The processing system of claim 5, whereinthe array status circuitry comprises: a bank register having a pluralityof bits corresponding to the plurality of blocks; an array statusregister to store array status data indicating where a write operationis performed on the array; and wherein the control circuitryautomatically provides array status data on the external dataconnections.
 7. The processing system of claim 3 wherein the array ofmemory cells are non-volatile memory cells.
 8. The processing system ofclaim 3, wherein the memory device is a synchronous flash memory device.9. A processing system, comprising: a first processor; a secondprocessor; and a memory device coupled to the first and secondprocessors, the memory device comprising: an array of memory cellsarranged in a plurality of addressable blocks; read/write circuitry toperform read and write operations on the array; memory status circuitryto output a memory status signal to external data connections inresponse to a request for a read operation on the array; and arraystatus circuitry to automatically couple memory write status data of aparticular block of the array to external data connections in responseto a read command on the particular block.
 10. The processing system ofclaim 9, and further comprising control circuitry to automaticallyprovide the array status data on the external data connections and toprovide the memory write status data on the external data connections inresponse to a memory status command.
 11. The processing system of claim9, wherein the array status circuitry comprises: a bank register havinga plurality of bits corresponding to the plurality of blocks; an arraystatus register to store array status data indicating where a writeoperation is performed on the array.
 12. The processing system of claim9, wherein the memory status circuitry comprises: a memory statusregister to store memory write status data indicating if data is beingwritten to the array of one of the plurality of non-volatileprogrammable registers.
 13. The processing system of claim 9 wherein thearray of memory cells are non-volatile memory cells.
 14. The processingsystem of claim 9, wherein the memory device is a synchronous flashmemory device.
 15. A processing system, comprising: a first processor; asecond processor; and a memory device coupled to the first and secondprocessors, the memory device comprising: an array of memory cellsarranged in a plurality of addressable blocks; and array statuscircuitry to automatically couple status data of a block of the array toexternal data connections in response to a read command on the block.16. The processing system of claim 15, wherein the array statuscircuitry comprises: a bank register having a plurality of bitscorresponding to the plurality of blocks; an array status register tostore array status data indicating where a write operation is performedon the array; and control circuitry to automatically provide arraystatus data on external data connections.
 17. The processing system ofclaim 16, and further comprising: memory status circuitry to output amemory status signal in response to a request for a read operation onthe array.
 18. The processing system of claim 17, wherein the memorystatus circuitry comprises: a memory status register to store memorywrite status data indicating if data is being written to the array ofone of the plurality of non-volatile programmable registers; and whereinthe control circuitry provides the memory write status data in responseto a memory status command.
 19. A processing system comprising; aplurality of processors; and a synchronous memory device coupled to theplurality of processors, the synchronous memory device comprising, anarray of memory cells arranged in a plurality of addressable blocks, abank register having a plurality of bits corresponding to the pluralityof blocks, an array status register to store status data indicatingwhere a write operation is performed on the array, control circuitry toperform a write operation on a first block of the plurality of blocks inresponse to a write command from a first processor of the plurality ofprocessors, and to automatically couple the status data to external dataconnections in response to a read command from a second processor of theplurality of processors.
 20. A processing system, comprising: aplurality of processors; and a synchronous memory device coupled to theplurality of processors, the synchronous memory device comprising: anarray of memory cells arranged in a plurality of addressable blocks; andmemory status circuitry to output a memory status signal in response toa request for a read operation on the array.
 21. The processing systemof claim 20, wherein the memory status circuitry comprises: a memorystatus register to store memory write status data indicating if data isbeing written to the array of one of the plurality of non-volatileprogrammable registers; and control circuitry to provide the memorywrite status data in response to a memory status command.
 22. Theprocessing system of claim 21, and further comprising: array statuscircuitry to automatically couple status data of a block of the array toexternal data connections in response to a read command on the block.23. The processing system of claim 22, wherein the array statuscircuitry comprises: a bank register having a plurality of bitscorresponding to the plurality of blocks; an array status register tostore array status data indicating where a write operation is performedon the array; and wherein the control circuitry automatically providesarray status data on the external data connections.
 24. A processingsystem, comprising: a plurality of processors; and a synchronous memorydevice coupled to the plurality of processors, the synchronous memorydevice comprising: an array of memory cells arranged in a plurality ofaddressable blocks; read/write circuitry to perform read and writeoperations on the array; memory status circuitry to output a memorystatus signal to external data connections in response to a request fora read operation on the array; and array status circuitry toautomatically couple memory write status data of a particular block ofthe array to external data connections in response to a read command onthe particular block.
 25. The processing system of claim 24, and furthercomprising control circuitry to automatically provide the array statusdata on the external data connections and to provide the memory writestatus data on the external data connections in response to a memorystatus command.
 26. A processing system, comprising: a plurality ofprocessors; and a synchronous memory device coupled to the plurality ofprocessors, the synchronous memory device comprising: an array of memorycells arranged in a plurality of addressable blocks; and array statuscircuitry to automatically couple status data of a block of the array toexternal data connections in response to a read command on the block.27. The processing system of claim 26, wherein the array statuscircuitry comprises: a bank register having a plurality of bitscorresponding to the plurality of blocks; an array status register tostore array status data indicating where a write operation is performedon the array; and control circuitry to automatically provide arraystatus data on external data connections.
 28. The processing system ofclaim 27, and further comprising: memory status circuitry to output amemory status signal in response to a request for a read operation onthe array.
 29. The processing system of claim 28, wherein the memorystatus circuitry comprises: a memory status register to store memorywrite status data indicating if data is being written to the array ofone of the plurality of non-volatile programmable registers; and whereinthe control circuitry provides the memory write status data in responseto a memory status command.